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ds07-12521-3e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89910 series mb89913/915/p915/pv910 n description the mb89910 series has been developed as a general-purpose version of the f 2 mc*-8l family consisting of proprietary 8-bit, single-chip microcontrollers. in addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as dual-clock control system, five operating speed control stages, timers, a serial interface, an a/d converter, a buzzer output, a low-voltage detection reset, high-voltage driver, a watch prescaler, and external interrupts. the mb89910 series is applicable to a wide range of applications from consumer products to industrial equipments. *: f 2 mc stands for fujitsu flexible microcontroller. n features ? minimum execution time: 0.50 m s/8.0 mhz oscillation ? interrupt processing time: 4.50 m s/8.0 mhz oscillation ?f 2 mc-8l family cpu core ? dual-clock control system (continued) n package multiplication and division instructions 16-bit arithmetic operations test and branch instructions bit manipulation instructions, etc. instruction set optimized for controllers (dip-48p-m01) (fpt-48p-m15) (mdp-64c-p02) 48-pin plastic sh-dip 48-pin plastic qfp 64-pin ceramic mdip
2 mb89910 series (continued) ? high-voltage ports (built-in a pull-down resistor capable) 8 ports for large current 10 ports for small current ? 8-bit pwm timer: 1 channel ? 16-bit timer/counter: 1 channel ? 21-bit timebase timer ? 8-bit serial i/o: 1 channel ? 8-bit a/d converter: 8 channels ? external interrupt edge detection function two channels, including one of which voltage can be applied from C0.3 to +7.0 v ? low-voltage detection reset (excluding the mb89pv910) ? low-power consumption modes (subclock mode, watch mode, sleep mode, and stop mode) ? reset output and power-on reset function ? watch prescaler
3 mb89910 series n product lineup (continued) partnumber parameter mb89913 mb89p915 mb89pv910 classification mass production product (mask rom product) one-time prom product piggyback/ evaluation product (for evaluation and development) rom size 8 k 8 bits (internal mask rom) 16 k 8 bits (internal mask rom) 16 k 8 bits (internal prom, programmable with general-purpose eprom programmer) 32k 8 bits (piggyback) (external rom) ram size 256 8 bits 512 8 bits 1 k 8 bits cpu functions number of instructions: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1, 8, 16 bits minimum execution time: 0.50 m s/8.0 mhz to 8.00 m s/8.0 mhz, or 61 m s/32.768 khz interrupt processing time: 4.5 m s/8.0 mhz to 72.0 m s/8.0 mhz, or 549.3 m s/32.768 khz note: the above times depend on the gear function. ports high-voltage output ports (p-ch open-drain): 8 (p10 to p17 for large current) 10 (p20 to p27 and p50 to p51 for small current) i/o ports (cmos): 13 (p00 to p07, p34 to p37, and p40) i/o ports (n-ch open-drain): 6 (p30 to p33, p41, p42) input ports (cmos): 2 (p60 and p61 also serve as a subclock pin) total: 39 timebase timer (timer 1) capable of generating four different intervals at 8.0-mhz oscillation: 0.26, 0.51, 1.02, and 524.0 ms 8-bit pwm timer (timer 2) 8-bit timer operation (square wave output capable. operation clock: 1, 2, 8, or 16 instruction cycles) 8-bit resolution pwm operation (conversion cycle: 128 m s to 2.0 ms at 8.0 mhz) 16-bit timer/counter (timer 3) 16-bit timer operation (operating clock: 1 instruction cycle) 16-bit event counter operation (rising/falling/both edges selectable) 8-bit serial i/o 8 bits lsb first/msb first selectable transfer clock (external, 4/8/16 instruction cycles) 8-bit a/d converter 8-bit resolution 8 channels a/d conversion mode (conversion time of 22.0 m s/8.0 mhz) sense mode (conversion time of 6.0 m s/8.0 mhz) continuous activation enabled by external clock or internal clock reference voltage input (avr) is provided. mb89915
4 mb89910 series (continued) * : varies with conditions such as the operating frequency. (see section n electrical characteristics.) in the case of the mb89pv910, the voltage varies with the ice or the eprom to be connected. n package and corresponding products : available : not available *1: under examination for development *2: available by conversion from mdip-64 to sh-dip-48 64sd-48sd-8l2: for conversion (mdp-64c-p02) ? dip-48p-m01 inquiry: sun hayato co., ltd.: tel: (81)-3-3986-0403 fax: (81)-3-5396-9106 note: for more information about each package, see section n package dimensions. partnumber parameter mb89913 mb89p915 mb89ppv910 external interrupt 2 independent channels (edge selection, interrupt vector, factor flag) rising/ falling/both edges selectable built-in analog noise canceller used also for wake-up stop/sleep modes. (edge detection is also permitted in stop mode.) low-voltage detection reset continuous operation (detection power supply voltage of 4.0 0.3 v, 3.6 0.3 v or 3.3 0.3 v) intermittent operation (activated for each watch interrupt under the dual-clock sys- tem) not available low-power consumption (standby mode) sleep mode, stop mode, and watch mode process cmos operating voltage* 3.8 v to 5.5 v 4.5 v to 5.5 v eprom for use ? mbm27c256a- 20cz package mb89913 mb89915 mb89p915 mb89pv910 dip-48p-m01 fpt-48p-m15 mdp-64c-p02 mb89915 * 1 * 2
5 mb89910 series n differences among products 1. memory size before evaluating using the piggyback product, verify its differences from the product that will actually be used. take particular care on the following points: ? the stack area, etc., is set at the upper limit of the ram. 2. current consumption ? in the case of the mb89pv910, add the current consumed by the eprom which is connected to the top socket. ? when operated at low speed, the product with an otprom (one-time prom) or an eprom will consume more current than the product with a mask rom. however, the current consumption in sleep/stop modes is the same. (for more information, see sections n electrical characteristics and n example characteristics.) 3. mask options functions that can be selected as options and how to designate these options vary by the product. before using options check section n mask options. take particular care on the following points: ? a pull-down resistor for p10 to p17, p20 to p27, and for p50 to p51 cannot be set for the mb89p915 and mb89pv910. the mb89915 and mb89913 allow a pull-down resistor to be set for individual pins. such pins on the mb89p915 and mb89pv910 are fixed to have no pull-down resistor. ? the low-voltage detection reset cannot be used on the mb89pv910. the voltage to be detected by the low- voltage detection reset is set by using a register for the mb89p915 and by using a mask option for the mb89915 and mb89913. if the detection voltage has been set to a lower value than the operating voltage, however, use the gear function to operate the device with the faster clock at a lower speed, or operate the device with the slower clock. note that the results of operation are unpredictable if the device is attempted to operate at a lower voltage than the operating voltage with the faster clock put in top gear.
6 mb89910 series n pin assignment ( dip-48p-m01 ) (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 av ss avr p37/an7 p36/an6 p35/an5 p34/an4 p33/an3 p32/an2 p31/an1 p30/an0 p07/sck p06/so p05/si p03/ec p00 p61/x1a p60/x0a p42 p41/int1 p40/int0 rst p04/pwo p02/adst p01/bz2 v cc p10 p11 p12 p13 p14 p15 p16 p17 vfdp p20 p21 p22 p23 p24 p25 p26 p27 p50 p51/bz1 test x1 x0 v ss 1 2 3 4 5 6 7 8 9 10 11 12 p33/an3 p32/an2 p31/an1 p30/an0 p07/sck p06/so p05/si p04/pwo p03/ec p02/adst p01/bz2 p00 36 35 34 33 32 31 30 29 28 27 26 25 p15 p16 p17 vfdp p20 p21 p22 p23 p24 p25 p26 p27 48 47 46 45 44 43 42 41 40 39 38 37 p34/an4 p35/an5 p36/an6 p37/an7 avr av ss v cc p10 p11 p12 p13 p14 13 14 15 16 17 18 19 20 21 22 23 24 under examination for development x1a/p61 x0a/p60 p42 p41/int1 p40/int0 rst v ss x0 x1 test p51/bz1 p50 (top view) (fpt-48p-m15)
7 mb89910 series ( mdp-64c-p02 ) (top view) 65 v pp 66 a12 67 a7 68 a6 69 a5 70 a4 71 a3 72 a2 73 a1 74 a0 75 o1 76 o2 77 o3 78 v ss v cc 92 a14 91 a13 90 a8 89 a9 88 a11 87 oe 86 a10 85 ce 84 o8 83 o7 82 o6 81 o5 80 o4 79 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 30 31 32 35 34 v cc p10 p11 p12 p13 p14 p15 p16 p17 vfdp p20 p21 p22 p23 p24 p25 p26 p27 p50 p51/bz1 test x1 x0 v ss n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. 33 av ss avr p37/an7 p36/an6 p35/an5 p34/an4 p33/an3 p32/an2 p31/an1 p30/an0 p07/sck p06/so p05/si p03/ec p00 p61/x1a p60/x0a p42 p41/int1 p40/int0 rst n.c. n.c. n.c. n.c. n.c. n.c. n.c. v ss p04/pwo p02/adst p01/bz2
8 mb89910 series n pin description (continued) *1: dip-48p-m01 *2: fpt-48p-m15 *3: mdp-64c-p02 pin no. pin name circuit type function sh- dip* 1 qfp* 2 mdip* 3 26 20 42 x0 a main clock crystal oscillator pins 27 21 43 x1 20 14 20 x0a/p60 i these pins can select either general-purpose cmos inputs or subclock oscillator pins by the mask options. when these pins are used as a general-purpose input pin, the pin is a hysteresis input with a built-in noise canceller. 19 13 19 x1a/p61 24 18 24 rst c reset i/o pin this pin is an n-ch open-drain output type with pull-up resistor and a hysteresis input type. l is output from this pin by an internal source. the internal circuit is initialized by the input of l. this pin is with a noise canceller. 18 12 18 p00 d general-purpose cmos i/o port this port input is a hysteresis input, with a built-in noise canceller. 17 11 17 p01/bz2 d general-purpose cmos i/o port this port input is a hysteresis input, with a built-in noise canceller. also serves as a buzzer output. 16 10 16 p02/adst d general-purpose cmos i/o port this port input is a hysteresis input, with a built-in noise canceller. also serves as the external activation pin for the a/d converter. 15 9 15 p03/ec d general-purpose cmos i/o port this port input is a hysteresis input, with a built-in noise canceller. also serves as the external clock input for the 16-bit timer/counter. 14 8 14 p04/pwo d general-purpose cmos i/o port this port input is a hysteresis input, with a built-in noise canceller. also serves as the pwm output for the 8-bit pwm timer. 13, 12 7, 6 13, 12 p05/si, p06/so d general-purpose cmos i/o ports these port inputs are a hysteresis input, with a built-in noise canceller. also serve as serial data outputs for the 8-bit serial interface. 11 5 11 p07/sck d general-purpose cmos i/o port this port input is a hysteresis input, with a built-in noise canceller. also serves as the serial transfer clock output for the 8-bit serial interface. 47 to 40 41 to 34 63 to 56 p10 to p17 g p-ch high-voltage open-drain output ports for large current
9 mb89910 series (continued) (continued) *1: ip-48p-m01 *2: fpt-48p-m15 *3: mdp-64c-p02 pin no. pin name circuit type function sh- dip* 1 qfp* 2 mdip* 3 38 to 31 32 to 25 54 to 47 p20 to p27 g p-ch high-voltage open-drain output ports for small current 10 to 7 4 to 1 10 to 7 p30/an0 to p33/an3 h general-purpose n-ch open-drain i/o ports these port inputs are a hysteresis input, each with a built-in noise canceller. although the pins are also serve as an analog inputs, an analog input does not pass through their noise cancellers. 6 to 3 48 to 45 6 to 3 p34/an4 to p37/an7 f general-purpose cmos i/o ports these port inputs are a hysteresis input, each with a built-in noise canceller. although the pins are also serve as an analog inputs, an analog input does not pass through their noise cancellers. 23 17 23 p40/int0 d general-purpose cmos i/o port this port input is a hysteresis input, with a built-in noise canceller. also serves as an external interrupt. external interrupt input passes through the noise canceller. 22 16 22 p41/int1 e general-purpose n-ch open-drain i/o port this port input is a hysteresis input, with a built-in noise canceller. also serves as an external interrupt. external interrupt input passes through the noise canceller. 21 15 21 p42 e general-purpose n-ch open-drain i/o port this port input is a hysteresis input, with a built-in noise canceller. 30 24 46 p50 g p-ch high-voltage open-drain output ports for small current 29 23 45 p51/bz1 g p-ch high-voltage open-drain output port for small current also serves as a buzzer output. 28 22 44 test b operating mode selection pin usually, connect to v ss directly. on the product with an eprom, the pin is the v pp pin. 39 33 55 vfdp voltage supply pin connected to a pull-down resistor for ports 1, 2, and 5 in products without a pull-down resistor, in the mb89p915, and in the mb89pv910, this pin should be left open.
10 mb89910 series (continued) *1: ip-48p-m01 *2: fpt-48p-m15 *3: mdp-64c-p02 pin no. pin name circuit type function sh- dip* 1 qfp* 2 mdip* 3 48 42 64 v cc power supply pin 25 19 32,41 v ss power supply (gnd) pin 1431av ss a/d converter power supply pin use this pin at the same voltage as v ss . 2 44 2 avr a/d converter reference voltage input pin
11 mb89910 series ? external eprom pins (mdip only) * : mdp-64c-p02 pin no. pin name i/o function mdip* 65 v pp o h level output pin 66 67 68 69 70 71 72 73 74 a12 a7 a6 a5 a4 a3 a2 a1 a0 o address output pins 75 76 77 o1 o2 o3 i data input pins 78 v ss o power supply (gnd) pin 79 80 81 82 83 o4 o5 o6 o7 o8 i data input pins 84 ce o rom chip enable pin outputs h during standby. 85 a10 o address output pin 86 oe o rom output enable pin outputs l at all times. 87 88 89 a11 a9 a8 o address output pin 90 a13 o 91 a14 o 92 v cc o eprom power supply pin
12 mb89910 series n i/o circuit type (continued) type circuit remarks a ? main clock at an oscillation feedback resistor of approximately 1 m w /5.0 v b c ? at an output pull-up resistor (p-ch) of approximately 50 k w /5.0 v ? cmos hysteresis input (with a noise canceller) d ? cmos i/o ? cmos hysteresis input (with a noise canceller) e ? n-ch open-drain i/o ? cmos hysteresis input (with a noise canceller) x1 x0 main clock control signal n-ch p-ch p-ch n-ch r hysteresis input (with a noise canceller) p-ch n-ch hysteresis input (with a noise canceller) n-ch h y steresis input ( with a noise canceller )
13 mb89910 series (continued) type circuit remarks f ? cmos output ? cmos hysteresis input (with a noise canceller excluding analog inputs) g ? p-ch high-voltage open-drain output ? at an output pull-down resistor of approximately 100 k w /5.0 v h ? n-ch open-drain output ? cmos hysteresis input (with a noise canceller excluding analog inputs) i ? subclock the oscillation feedback resistor is built only in the mb89pv910. ? cmos hysteresis input (with a noise canceller) when no subclock is being used p-ch n-ch hysteresis input (with a noise canceller) analog input port vfdp p-ch n-ch hysteresis input (with a noise canceller) analog input x1a x0a hysteresis input (with a noise canceller) hysteresis input (with a noise canceller) port port port subclock control signal n-ch p-ch
14 mb89910 series n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of power supply pins on microcontrollers with a/d and d/a converters connect to be av cc = davc = v cc and av ss = avr = v ss even if the a/d and d/a converters are not in use. 4. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 5. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 6. precautions when using an external clock when an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode.
15 mb89910 series n programming to eprom on the mb89p915 the mb89p915 is an otprom version of the mp89910 series. 1. features ? 16-kbyte prom on chip 2. memory space memory space in each mode such as 16-kbyte prom mode is diagrammed below. 3. programming to the eprom since the mb89p915 requires a special method for programming to its prom, the types of general-purpose eprom programmers applicable to the mb89p915 are limited. programming to the prom on the mb89p915 requires an eprom programmer applicable to the mb89p915 and a dedicated adapter. when the operating rom area for a single chip is 16 kbytes (c000 h to ffff h ) the prom can be programmed as follows: ? programming procedure (1) set the eprom programmer to the mb89p195. (2) load program data into the eprom programmer at 4000 h to 7fff h . (note that addresses 0c000 h to 0ffff h in the operation mode correspond to 4000 h to 7fff h in eprom mode.) (3) program with the eprom programmer. ffff h 0000 h c000 h 8000 h 7fff h 0000 h 4000 h ram i/o program area (prom) 16 kb mb89p915 not available (corresponding addresses on the eprom programmer) eprom mode not available (read value ff h ) 0080 h 0280 h program area (prom) 16 kb free space (read value ff h )
16 mb89910 series 4. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. 5. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. 6. eprom programmer socket adapter and recommended programmer manufacturer inquiry: sun hayato co., ltd.: tel: (81)-3-3986-0403 fax: (81)-3-5396-9106 data i/o co., ltd.: tel: usa/asia (1)-206-881-6444 europe (49)-8-985-8580 part no. package compatible socket adapter sun hayato co., ltd. recommended programmer manufac- turer and programmer name data i/o co., ltd. unisite (ver.5.0 or later) 3900 (ver.2.8 or later) 2900 (ver.3.8 or later) mb89p915p-sh sh-dip-48 rom-48qf2-28dp-8l recommended program, verify aging +150 c, 48 hrs. data verification assembly
17 mb89910 series n programming to the eprom with piggyback/evaluation device 1. eprom for use mbm27c256a-20cz 2. programming socket adapter any special programming adapter is not required since the package for the eprom to be used is dip-28. 3. memory space eprom memory space and the memory space on the mb89pv910 are diagrammed below. 4. programming to the eprom (1) set the eprom programmer to the mbm27c256a-20cz. (2) load program data into the eprom programmer at 0000 h to 7fff h . (note that addresses 08000 h to 0ffff h in the operation mode correspond to 0000 h to 7fff h in the eprom mode.) (3) program with the eprom programmer. ffff h 0000 h 8000 h mb89pv910 ram 7fff h 0000 h i/o mbm27c256a-20cz program area 32 kb not available 0080 h 0480 h program area (eprom) 32 kb
18 mb89910 series n block diagram x0 x1 x0a/p60 p04/pwo p05/si p06/so p07/sck p00 p02/adst p01/bz2 p50 p20 to p27 p10 to p17 x1a/p61 avr av ss vfdp p51/bz1 p03/ec p42 p41/int1 p40/int0 clock controller subclock oscillator (32.768 khz) main clock oscillator internal bus port 6 cmos input port rst timebase timer low-voltage detection reset n-ch open-drain i/o port port 3 8-bit a/d converter port 3 cmos i/o port ram rom v cc , v ss , test other pins f 2 mc-8l cpu external interrupt n-ch open-drain output port port 4 port 4 cmos i/o port 8-bit pwm timer buzzer output buzzer output cmos i/o port 16-bit timer/counter 8-bit serial i/o port 0 watch prescaler high-voltage output port 5 high-voltage output port 2 high-voltage output port 1 8 8 p30/an0 to p33/an3 p34/an4 to p37/an7 4 4 reset circuit (watchdog timer)
19 mb89910 series n cpu core 1. memory space the microcontrollers of the mb89910 series offer a memory space of 64 kbytes for storing all of i/o, data, and program areas. the i/o area is located the lowest address. the data area is provided immediately above the i/ o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. memory space 0000 h 0080 h 0100 h 0200 h 8000 h ffff h mb89pv910 i / o ram 1 kb 0000 h 0080 h 0100 h 0200 h c000 h mb89p915 mb89915 i / o ram 512 b 0280 h 0480 h ffff h external rom 32 kb not available not available register register rom* 16 kb 0000 h 0080 h 0100 h 0180 h e000 h ffff h mb89913 i / o rom 8 kb not available register *: this is an internal prom on the mb89p915.
20 mb89910 series 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following registers are provided: program counter (pc): a 16-bit register for indicating instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h indeterminate indeterminate indeterminate indeterminate indeterminate i-flag = 0, il1, 0 = 11 the other bit values are indeterminate. initial value structure of the program status register vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr vacancy vacancy
21 mb89910 series the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set to 1 when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared to 0 otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is enabled when this flag is set to 1. interrupt is disabled when the flag is cleared to 0. cleared to 0 at the reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set to 1 if the msb becomes to 1 as the result of an arithmetic operation. cleared to 0 when the bit is cleared to 0. z-flag: set to 1 when an arithmetic operation results in 0. cleared to 0 otherwise. v-flag: set to 1 if the complement on 2 overflows as a result of an arithmetic operation. cleared to to 0 if the overflow does not occur. c-flag: set to 1 when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared to 0 otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 rp generated addresses lower op codes
22 mb89910 series the following general-purpose registers are provided: general-purpose registers: an 8-bit resister for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers and up to a total of 32 banks can be used on the mb89915. the bank currently in use is indicated by the register bank pointer (rp). register bank configuration this address = 0100 h + 8 (rp) memor y area 32 banks r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7
23 mb89910 series n i/o map (continued) address read/write register name register description 00 h (r/w) pdr0 port 0 data register 01 h (w) ddr0 port 0 data direction register 02 h vacancy 03 h vacancy 04 h vacancy 05 h vacancy 06 h vacancy 07 h (r/w) sycc system clock control register 08 h (r/w) stbc standby control register 09 h (r/w) wdtc watchdog timer control register 0a h (r/w) tbcr time-base timer control register 0b h (r/w) wpcr watch prescaler control register 0c h (r/w) pdr3 port 3 data register 0d h (w) ddr3 port 3 direction register 0e h (r/w) buzr buzzer register 0f h (r/w) eic external interrupt control register 10 h (r/w) pdr1 port 1 data register 11 h (r/w) pdr2 port 2 data register 12 h (r/w) pdr5 port 5 data register 13 h (r) pdr6 port 6 data register 14 h (r/w) pdr4 port 4 data register 15 h (w) ddr4 port 4 direction register 16 h (w) comr pwm compare register 17 h (r/w) cntr pwm control register 18 h (r/w) tmcr 16-bit timer control register 19 h (r/w) tchr 16-bit timer control register (h) 1a h (r/w) tclr 16-bit timer control register (l) 1b h vacancy 1c h (r/w) smr serial mode register 1d h (r/w) sdr serial data register 1e h (r/w) adc1 a/d converter control register 1 1f h (r/w) adc2 a/d converter control register 2
24 mb89910 series (continued) note: do not use vacancies. address read/write register name register description 20 h (r/w) adcd a/d converter data register 21 h vacancy 22 h (w) pcr port input control register 23 h (r/w) lvrc low-voltage detection reset control register 24 h to 7b h vacancy 7c h (w) ilr1 interrupt level setting register 1 7d h (w) ilr2 interrupt level setting register 2 7e h (w) ilr3 interrupt level setting register 3 7f h vacancy
25 mb89910 series n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) (continued) parameter symbol value unit remarks min. max. power supply voltage v cc avr v ss C 0.3 v ss + 7.0 v avr v cc + 0.3* 1 v pp C 0.6 13.0 v vfdp v cc C 40 v cc + 0.3 v input voltage v i1 v ss C 0.3 v cc + 0.3 v except p41* 2 v i2 v ss C 0.3 7.0 v p41 output voltage v o1 v ss C 0.3 v cc + 0.3 v except p10 to p17, p20 to p27, p50, p51* 2 v o2 v cc C 40.0 v cc + 0.3 v p10 to p17, p20 to p27 p50, p51 h level total maximum output current ? i oh ? C120 ma h level total average output current ? i ohav ? C90 ma average value (operating current operating rate) h level maximum output current i oh ? C12 ma p00 to p07, p34 to p37, p40 ? C20 ma p20 to p27, p50, p51 ? C36 ma p10 to p17 h level average output current i ohav ? C6 ma p00 to p07, p34 to p37, p40 average value (operating current operating rate) ? C10 ma p20 to p27, p50, p51 average value (operating current operating rate) ? C20 ma p10 to p17 average value (operating current operating rate) l level total maximum output current ? i ol ? 36 ma l level total average output current ? i olav ? 20 ma average value (operating current operating rate) l level maximum output current i ol ? 10 ma p00 to p07, p30 to p37, p40 to p47 l level average output current i olav ? 4ma
26 mb89910 series (continued) (av ss = v ss = 0.0 v) *1: take care so that avr does not exceed v cc + 0.3 v and v cc does not exceed v cc , such as when power is turned on. *2: v i and v o must not exceed v cc + 0.3 v. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, tem- perature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. 2. recommended operating conditions (av ss = v ss = 0.0 v) * : these values vary with the operating frequency, instruction cycle, and analog assurance range. see figure 1 and 5. a/d converter electrical characteristics. parameter symbol value unit remarks min. max. power consumption p d 440 mw sh-dip: dip-48-m01 360 mw qfp: fpt-48-m15 operating temperature t a C40 +85 c storage temperature tstg C55 +150 c parameter symbol value unit remarks min. max. power supply voltage v cc 4.5* 5.5* v normal operation assurance range*(mb89pv910) 3.8* 5.5* v normal operation assurance range*(mb89p915/915/913) 2.7 5.5 v watch mode, sub-run mode 1.5 5.5 v retains the ram state in stop mode a/d converter reference input voltage avr 0.0 v cc v high-voltage pull-down resistor supply voltage vfdp v cc C 35.0 v cc + 0.3 v operating temperature t a C40 +85 c
27 mb89910 series figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/f ch . since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. 1 2 3 4 5 6 2.0 6.0 3.0 4.0 5.0 7.0 8.0 9.0 10.0 2.0 0.66 1.3 1.0 0.8 0.57 0.5 0.44 0.4 operation assurance range operating voltage (v) main clock operating frequency (at an instruction cycle of 4/f ch ) (mhz) minimum execution time (instruction cycle) ( m s) figure 1 operating voltage vs. main clock operating frequency
28 mb89910 series 3. dc characteristics (avr = v cc = +5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter sym- bol pin name condition value unit remarks min. typ. max. h level input voltage v ihs p00 to p07, p30 to p37, p40 to p42, p60, p61 x0, rst x1, test 0.8 v cc v cc + 0.3 v l level input voltage v ils p00 to p07, p30 to p37, p40 to p42, p60, p61 x0, rst x1, test v ss - 0.3 0.2 v cc v open-drain output pin application voltage v d1 p30 to p33, p42 v ss - 0.3 v cc + 0.3 v v d2 p41 v ss - 0.3 7.0v h level output voltage v oh1 p00 to p07, p30 to p37, p40 to p42, p60, p61 i oh = C2.0 ma 2.4 v excluding p30 to p33 and p41, p42 v oh2 p20 to p27, p50, p51 i oh = C10 ma 3.0 v v oh3 p10 to p17 i oh = C20 ma 3.0 v l level output voltage v ol1 p00 to p07, p30 to p37, p40 to p42, p60, p61 i ol = 1.8 ma 0.4 v v ol2 rst ,i ol = 4.0 ma 0.6 v input leakage current i li1 p00 to p07, p30 to p37, p40 to p42, p60, p61 0 < v i < v cc 5 m a output leakage current i lo1 p20 to p27, p50, p51 v i = vfdp C10 m a vfdp = v cc C 35.0 v i lo2 p10 to p17 v i = vfdp C20 m a vfdp = v cc C 35.0 v pull-up resistance r pull rst ,v in = 0.0 v 25 50 100 k w pull-down resistance r pd p10 to p17, p20 to p27, p50, p51 v in = 5.0 v 50 100 150 k w assuming the pull-down resistor option selected
29 mb89910 series (continued) (avr = v cc = +5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter sym- bol pin name condition value unit remarks min. typ. max. power supply current *1 when low- voltage detection reset operation is enabled, i lv d is added to each power supply current. i cc1 v cc f ch = 8 mhz v cc = 5.0 v t inst *2 = 0.5 m s when a/d conversion is stopped 10.0 18.0 ma mb89p915 915ma mb89913/ 915/pv910 i cc2 f ch = 8 mhz v cc = 3.8 v t inst *2 = 8.0 m s when a/d conversion is stopped 3.0 6.0 ma mb89p915 1.8 2.4 ma mb89913/ 915/pv910 i cs1 f ch = 8 mhz v cc = 5.0 v t inst *2 = 0.5 m s when a/d conversion is stopped 3 7ma i cs2 f ch = 8 mhz v cc = 3.8 v t inst *2 = 8.0 m s when a/d conversion is stopped 1.21.8ma i csb f cl = 32 khz v cc = 3.0 v subclock mode 1.2 3.6 ma mb89p915 60 180 m a mb89913/ 915/pv910 i cs3 f cl = 32 khz v cc = 3.0 v subclock sleep mode 3264 m a i cct f cl = 32 khz v cc = 3.0 v watch mode main clock stop mode at dual- clock system 420 m a i cca f ch = 8 mhz t a = +25 c v cc = 5.0 v t inst *2 = 0.5 m s when a/d conversion is activated 12.5 22.5 ma sleep mode
30 mb89910 series (continued) (avr = v cc = +5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) *1: the power supply current is measured at external clock. *2: for information on t inst , see (4) instruction cycle in 4. ac characteristics. parameter sym- bol pin name condition value unit remarks min. typ. max. power supply current *1 when low- voltage detection reset operation is enabled, i lv d is added to each power supply current. i cch v cc f cl = 32.678 khz, v cc = 3.0 v t a = +25 c, subclock stop mode main clock stop mode at single clock system 10 m a i lv d v cc = 5.0 v t a = +25 c, subclock stop mode main clock stop mode at single clock system 60 120 m a power consumption of low-voltage detection reset i r avr f ch = 8 mhz, t a = +25 c, when a/d conversion is activated 200 m a i rh avr f ch = 8 mhz, t a = +25 c, when a/d conversion is stopped 10 m a input capacitance c in other than av ss , avr, v cc , and v ss f = 1 mhz 10 pf
31 mb89910 series 4. ac characteristics (1) reset timing (avr = v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: t xcyl is the oscillation period (1/f ch ) to input to the x0. (2) power-on reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol condition value unit remarks min. typ. max. rst l pulse width t zlzh 48 t xcyl ns rst noise limit width t zlnc 305080ns parameter symbol condition value unit remarks min. max. power supply rising time t r 50 ms power-on reset function only power supply cut-off time t off 1 ms due to repeated operations 0.2 v cc 0.2 v cc rst t zlzh t zlnc 0.2 v 0.2 v 2.0 v v cc 0.2 v t r t off
32 mb89910 series (3) clock timing (av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition value unit remarks min. typ. max. clock frequency f ch x0, x1 2 8 mhz f cl x0a, x1a 32.768 khz clock cycle time t xcyl x0, x1 125 500 ns t lxcyl x0a, x1a 30.5 m s input clock pulse width p wh p wl x0 30 ns external clock p whl p wll x0a 15.2 m s input clock rising/falling time t cr t cf x0, x0a 10 ns external clock 0.2 v cc 0.8 v cc x0 0.2 v cc t cr t cf 0.8 v cc 0.2 v cc x0 x1 x0 x1 c0 c1 t xcyl p wh p wl when a crystal or ceramic resonator is used when an external clock is used open x0 and x1 timing and conditions main clock conditions
33 mb89910 series (4) instruction cycle note: when operating at 8 mhz, the cycle varies with the execution time. parameter symbol value (typical) unit remarks instruction cycle (minimum execution time) t inst 4/f ch , 8/f ch , 16/f ch , 32/f ch m s operation at f ch = 8 mhz; (4/f ch )t inst = 0.5 m s 2/f cl m s operation at f cl = 32.768 khz; (4/f ch )t inst = 61.036 m s 0.2 v cc 0.8 v cc x0a 0.2 v cc t cr t cf 0.8 v cc 0.2 v cc x0a x1a x0a x1a x0a x1a mb89pv910 mb89913/915/p915 c0 c1 c0 c1 t lxcyl p whl when a crystal or ceramic resonator is used when an external clock is used p wll when a crystal or ceramic resonator is used r f r d open x0a and x1a timing and conditions subclock conditions
34 mb89910 series (5) low-voltage detection reset (av ss = v ss 0.0 v, t a = C40 c to +85 c) parameter symbol condition value unit remarks min. max. detection voltage at power supply voltage fall v dl1 3.00 3.60 v v dh and v dl are set for the mb89913/915 by mask options and for the mb89p915 by a register. v dl2 3.30 3.90 v v dl3 3.70 4.40 v detection voltage at power supply voltage rise v dh1 3.10 3.80 v v dh2 3.40 4.10 v v dh3 3.80 4.60 v hysteresis width d v 0.10 v reset insensitive time t l 0.3 m s reset sensitive width t lw 16 t xcyl ns reset detection delay time t d 2.0 m s voltage regulation (v d /t d ) vcr 0.10 v/ m s d v t d v d t d run reset v dh v dl run reset t t v cc v dh v dl v cc power supply voltage t osc t osc t d power supply voltage t l or less t lw or less t osc oscillation stabilization time 2 18 = 32.8 ms (f ch = 8 mhz) reset not applied reset applied
35 mb89910 series (6) serial i/o timing (avr = v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc sck internal shift clock mode 2 t inst * m s sck ? so time t slov sck, so C200 200 ns valid si ? sck - t ivsh si, sck 1/2 t inst * m s sck - ? valid si hold time t shix sck, si 1/2 t inst * m s serial clock h pulse width t shsl sck external shift clock mode 1 t inst * m s serial clock l pulse width t slsh sck 1 t inst * m s sck ? so time t slov sck, so 0 200 ns valid si ? sck - t ivsh si, sck 1/2 t inst * m s sck - ? valid si hold time t shix sck, si 1/2 t inst * m s
36 mb89910 series internal shift clock mode external shift clock mode 0.8 v 2.4 v 2.4 v t slov 0.2 v cc 0.8 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc sck so si t scyc t ivsh t shix t slsh 2.4 v t slov 0.2 v cc t shix 0.8 v cc 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc sck so si t shsl 0.8 v cc 0.2 v cc 0.2 v cc
37 mb89910 series (7) peripheral input timing (avr = v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst, see (4) instruction cycle. (8) peripheral input noise limit width (avr = v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: the minimum rating is always cancelled, while values equal to or greater than maximum ratings are not cancelled. parameter symbol pin name condition value unit remarks min. max. peripheral input h level pulse width t ilih ec, adst int0, int1 2 t inst * m s peripheral input l level pulse width t ihil ec, adst int0, int1 2 t inst * m s parameter symbol pin name value unit remarks min. typ. max. peripheral input h level noise limit width 1 t ihnc1 all inputs excluding int1 and int0 71530ns mb89pv910 mb89p915 15 30 60 ns mb89913/ 915 peripheral input l level noise limit width 1 t ilnc1 all inputs excluding int1 and int0 71530ns mb89pv910 mb89p915 15 30 60 ns mb89913/ 915 peripheral input h level noise limit width 2 t ihnc2 int1, int0 30 50 100 ns mb89pv910 mb89p915 50 100 250 ns mb89913/ 915 peripheral input l level noise limit width 2 t ilnc2 int1, int0 30 50 100 ns mb89pv910 mb89p915 50 100 250 ns mb89913/ 915 0.2 v cc 0.8 v cc t ihil 0.8 v cc int0, int1 ec adst 0.2 v cc t ilih 0.2 v cc 0.8 v cc 0.8 v cc 0.2 v cc t ihnc2 t ihnc1 t ilnc2 t ilnc1 p00 to p07, p30 to p37, p40 to p42, p60, p61, sck, si, ec int0, int1 adst
38 mb89910 series 5. a/d converter electrical characteristics (v cc = +3.8 v to +5.5 v, f = 8 mhz, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle in 4. ac characteristics. 6. a/d converter glossary ? resolution analog changes that are identifiable with the a/d converter when the number of bits is 8, analog voltage can be divided into 2 8 = 256. ? linearity error (unit: lsb) the deviation of the straight line drawn connecting the zero transition point (0000 0000 ? 0000 0001) with the full-scale transition point (1111 1111 ? 1111 1110) from actual conversion characteristics ? differential linearity error (unit: lsb) the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value ? total error (unit: lsb) the difference between theoretical and actual conversion values parameter sym- bol pin name condition value unit remar ks min. typ. max. resolution 8bit total error 3.0 lsb linearity error 1.0 lsb differential linearity error 0.9 lsb zero transition voltage v ot an0 to an7 av ss C 1.5 lsb av ss +0.5 lsb av ss + 2.5 lsb mv full-scale transition voltage v fst an0 to an7 avr C 3.5 lsb avr C 1.5 lsb avr +0.5 lsb mv interchannel disparity 1.0 lsb a/d mode conversion time 44 t inst * m s sense mode conversion time 12 t inst * m s analog port input current i ain an0 to an7 avr = v cc = 5.0 v 10 m a analog input voltage an0 to an7 0.0 avr v reference voltage avr 3.4 av cc v reference voltage supply current i r avr avr = 5.0 v 200 m a
39 mb89910 series 7. notes on using a/d converter ? input impedance of the analog input pins the a/d converter used for the mb89910 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating a/d conversion. for this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. therefore, it is recommended to keep the output impedance of the external circuit low. if a higher accurancy is required, set the output impedance in this series to 2 k w or less . note that if the impedance cannot be kept low output impedance, it is recommended either to use the software to continuously activate the a/d converter for simulating longer sampling time or to connect an external capacitor of approx. 0.1 m f to the analog input pin. ? error the smaller the | avr C av ss |, the greater the error would become relatively. 1111 1111 1111 1110 0000 0010 0000 0001 0000 0000 v ot v nt v (n + 1)t v fst digital output (1 lsb n + v ot ) analog input actual conversion value theoretical conversion value linearity error 1 lsb 1 lsb = avr 256 linearity error = differential linearity error = total error = v nt ?(1 lsb n + v ot ) 1 lsb v ( n + 1 ) t ?v nt 1 lsb ?1 v nt ?(1 lsb n + 0.5 lsb) sample hold circuit analog channel selector close for 8 instruction cycles after activating a/d conversion. if the output impedance of external circuit is high , it is recommended to connect an external capacitor of approx. 0.1 m f. analog input pin comparator r = 6 k w . . c = 33 pf . . analog input equivalent circuit
40 mb89910 series n example characteristics (3) h level input voltage/l level input voltage (hysteresis input) 010 123456789 0.1 0.2 0.3 0.4 0.5 v ol (v) v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 6.0 v i ol (ma) 0.0 t a = +25 c v ol vs. i ol v cc = 5.0 v 0.0 1.0 v cc ?v oh (v) v cc = 2.5 v v cc = 3.0 v v cc = 6.0 v i oh (ma) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 ?.5 ?.0 ?.5 ?.0 ?.5 ?.0 t a = +25 c v cc ?v oh vs. i oh v cc = 4.0 v v cc = 5.0 v (1) l level output voltage (2) h level output voltage 012 3 456 7 v cc ( v ) 5.0 v in (v) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v ihs v ils t a = +25 c cmos hysteresis input v ihs : threshold when input voltage in hysteresis characteristics is set to h level v ils : threshold when input voltage in hysteresis characteristics is set to l level
41 mb89910 series (4) power supply current (external clock) (continued) 2.0 3.0 4.0 5.0 6.0 7.0 16 14 12 10 8 6 4 2 0 v cc (v) f ch = 8 mhz t a = +25 c divide by 4 (i cc1 ) divide by 64 (i cc2 ) i cc1 ,i cc2 (ma) 2.0 3.0 4.0 5.0 6.0 7.0 4.0 3.0 2.0 1.0 0 v cc (v) i cs , i cs2 (ma) i cc1 vs. v cc , i cc2 vs. v cc i cs1 vs. v cc , i cs2 vs. v cc 2.0 3.0 4.0 5.0 6.0 7.0 200 180 160 140 120 100 80 60 0 v cc ( v ) i csb ( a) 2.0 3.0 4.0 5.0 6.0 7.0 50 30 20 10 0 v cc ( v ) i cs3 ( a) i csb vs. v cc 40 20 40 i cs3 vs. v cc f ch = 8 mhz t a = +25 c t a = +25 c t a = +25 c divide by 4 (i cs1 ) divide by 64 (i cs2 )
42 mb89910 series (continued) (5) pull-up resistance 2.0 3.0 4.0 5.0 6.0 7.0 32 28 24 20 16 12 8 4 0 v cc (v) i cct ( a) i cct vs. v cc 36 2.0 3.0 4.0 5.0 6.0 7.0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 v cc (v) i cch ( a) i cch vs. v cc 1.8 t a = +25 c t a = +25 c 1,000 500 100 50 10 1234567 v cc (v) r pull (k w ) t a = +85 c t a = +25 c t a = ?0 c r pull vs. v cc
43 mb89910 series n instructions execution instructions can be divided into the following four groups: ? transfer ? arithmetic operation ? branch ? others table 1 lists symbols used for notation of instructions. table 1 instruction symbols (continued) symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits)
44 mb89910 series (continued) columns indicate the following: mnemonic: assembler notation of an instruction ~: number of instructions #: number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah immediately before the instruction is executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f. symbol meaning ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
45 mb89910 series table 2 transfer instructions (48 instructions) notes: during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
46 mb89910 series table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c ? ? ?? a c
47 mb89910 series (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) + off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
48 mb89910 series n instruction map l h 0123456789 abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor @a,ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d8 cmp @ep,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel
49 mb89910 series n mask options n ordering information no. part number mb89pv910 mb89913 mb89915 mb89p915 C101 C102 C101 C102 specifying procedure setting not possible setting not possible specify when ordering masking setting not possible setting not possible 1 selection either single or dual clock single-clock mode dual-clock mode single clock dual clock selectable single clock dual clock 2 pull-down resistors p17 to p10 p27 to p20 p51, p50 all pins fixed to without pull-down resistor can be selected per pin. all pins fixed to without pull-down resistor 3 voltage to be detected for low- voltage detection reset 3.3 0.3 v 3.6 0.3 v 4.0 0.3 v cannot be used. selectable can be set by register. part number package remarks MB89913P-SH mb89915p-sh mb89p915p-101-sh mb89p915p-102-sh 48-pin plastic sh-dip (dip-48p-m01) mb89913pf mb89915pf mb89p915pf-101 mb89p915pf-102 48-pin plastic qfp (fpt-48p-m15) mb89pv910c-101-es-sh mb89pv910c-102-es-sh 64-pin ceramic mdip (mdp-64c-p02)
50 mb89910 series n package dimensions +0.50 C0 C0 +.020 C.012 +.008 C0.30 +0.20 0.51(.020)min min max 40.894(1.610)ref index-2 15max typ 15.24(.600) (.010.002) 0.250.05 max 1.778(.070) (.070.007) 1.7780.18 1.00 .039 (.018.004) 0.450.10 3.00(.118) 5.25(.207) index-1 (.543.010) 13.800.25 1.720 43.69 1994 fujitsu limited d48002s-3c-3 c dimensions in mm (inches) 48-pin plastic sh-dip (dip-48p-m01)
51 mb89910 series (continued) 48-pin plastic qfp (fpt-48p-m15) +0.05 C0.01 +.002 C.0004 +0.30 C0.10 +.012 C.004 0.15 .006 12.00 .472 0.05(.002)min (stand off) "b" (.033.012) 0.850.30 0~10 0.15(.006)max 0.50(.020)max 0.20(.008) 0.15(.006) "a" sq sq (.602.016) lead no. 0.80(.0315)typ 48 13 24 37 36 25 1 12 details of "b" part index 0.10(.004) ref (.346) (.535.016) 8.80 13.600.40 2.70(.106)max m 0.16(.006) (.012.002) 0.300.06 15.300.40 details of "a" part 1994 fujitsu limited f48025s-1c-1 c dimensions in mm (inches)
52 mb89910 series (continued) 64-pin ceramic mdip (mdp-64c-p02) +0.13 C0.08 +.005 C.003 index area 0~9 (.750.012) 19.050.30 0.46 .018 (2.240.025) (.010.002) 0.250.05 (.050.010) 1.270.25 (.135.015) 3.430.38 55.12(2.170)ref (.035.005) 0.900.13 (.070.010) 1.7780.25 10.16(.400)max 33.02(1.300)ref (.100.010) 2.540.25 (.738.012) 18.750.30 typ 15.24(.600) 56.900.64 1994 fujitsu limited m64002sc-1-4 c dimensions in mm (inches)
53 mb89910 series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia pacific fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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